//-----------------------------------------------
//    module name: 
//    author:  Liang
//  
//    version: 1st version (2021-10-01)
//    description: 
//        
//
//
//-----------------------------------------------
`timescale 1ns / 1ps

module perip_slot(

    input  wire         clk,
    input  wire         rstn,

    output wire         outR,
    input  wire         inR,
    output reg  [50:0]  data_to,
    input  wire [50:0]  data_from,
    output wire         inA,
    input  wire         outA,

    output wire          we,
    output reg [31:0]   addr_i,
    output reg [31:0]   data_i,
    input  wire [31:0]  data_o
    
    );
    
`ifdef DC_ENV
    reg we_r;
    wire fireIn,fireIn2,outR0,outA0,outR1,outA1,outR2,outA2,sendtrig,fireout,req,rise;
    
    always @(posedge fireIn or negedge rstn) begin
        if(!rstn) begin
             addr_i <= 32'b0;
             data_i <= 32'b0;
             we_r   <= 1'b0;
        end else begin
             we_r <= data_from[50];
             addr_i <= {24'b0,data_from[49:42]};
             data_i <= data_from[41:10];
        end
    end
    posClick click0(.inR(inR), .inA(inA), .outR(outR0), .outA(outA0), .fire(fireIn), .rst(rstn));
    bidirDelay8U delay0(.inR(outR0), .inA(outA0), .outR(outR1), .outA(outA1));
    posClick click1(.inR(outR1), .inA(outA1), .outR(outR2), .outA(outA2), .fire(fireIn2), .rst(rstn));
    natSink receiver0(.inR(outR2), .inA(outA2));

    contTap sender(.trig(fireIn2 & ~we_r), .req(req), .rst(rstn));
    posClick click2(.inR(req),  .outR(outR), .outA(outA), .fire(fireout), .rst(rstn));
    fire2SyncPluse f2p_we(.fire(fireIn),.clk(clk),.rstn(rstn),.rise(rise));   

    always @(posedge fireout or negedge rstn) begin
        if(!rstn) begin
             data_to <= 1'b0;
        end else begin
             data_to <= {1'b0,addr_i,data_o,10'b0};
        end
    end

    assign we = we_r & rise;
`else
       assign inA = inR;
        
        reg  state;
        reg r_inR,r_outR;
        localparam      IDLE = 1'b0;
        localparam      WAIT = 1'b1;

    `ifdef BUS_BY_FUTONG         //ASIC DELY
        wire delay; 
        delay2U delay1(.inR(r_outR),.outR(delay));
        delay2U delay2(.inR(delay),.outR(outR));
    `else // USE LUT DELAY
    `ifndef POST_SYNTHSIS_SIMULATION
        assign #3 outR = r_outR ;
    `else 
        wire delay;   
        (* dont_touch = "true" *)
        LUT1 #(.INIT(2'b10)) delay1(
               .O(delay),   
               .I0(r_outR)      
            );
        (* dont_touch = "true" *)    
        LUT1 #(.INIT(2'b10)) delay2(
              .O(outR),   
              .I0(delay)      
           );
     `endif  
    `endif

        wire fire = inR != r_inR;
        always @(posedge clk or negedge rstn) begin
            if(!rstn) begin
                r_outR <= 0;
                data_to <= 0;
                r_inR <= 0;
                state <= 0;
                we <= 0;
                addr_i <= 0;
                data_i <=0;
            end
            else begin
                    r_inR <= inR;
                    case(state)
                        IDLE: begin 
                                    if(fire) begin
                                        we     <= data_from[50];
                                        addr_i <= {24'b0,data_from[49:42]};
                                        data_i <= data_from[41:10];
                                        state  <= data_from[50] ? IDLE:WAIT;
                                    end else begin
                                        state  <=    IDLE;
                                        we     <=    1'b0;
                                    end
                                end
                        WAIT: begin 
                                    we <= 1'b0;
                                    r_outR <= ~r_outR;
                                    data_to <= {1'b0,data_from[49:42],data_o,10'b0};
                                    state <= IDLE;
                                end
                    endcase
                end
        end
`endif
endmodule    
